Technical Field
The present invention relates to the field of memory configuration, and in particular, to a configuration structure and method of a block memory based on Field Programmable Gate Array (referred as FPGA).
Related Art
In the prior art, a block memory cannot have its read width and write width configured independently, has a limited width, and has not provided with functions of error checking and correcting and FIFO. If the block memory is to be expanded, additional logic resources have to be consumed, resulting in a restricted use of the block memory.